By and large, a so-called output buffer is provided at an output part of a semiconductor integrated circuit, such as a microcomputer or a system LSI, as an interface for an externally provided device. An inverter circuit is used as this output buffer. For example, a CMOS (Complementary MOS) inverter, made up by the combination of a P-channel MOS (Metal Oxide Semiconductor) transistor and an N-channel MOS transistor, has so far been known and used. The JP Patent Kokai Publication No. JP-P2002-314394A, for example, discloses a CMOS based output buffer capable of controlling the bufferability of the output buffer.
In the manufacture process for a semiconductor integrated circuit, a variety of accelerated tests are conducted for eliminating infant defects and for stabilizing the performance. In the gazette of JP Patent Kokai Publication No. JP-A-7-58172, there is introduced a universal burn-in board for conducting a burn-in test for a packaged semiconductor integrated circuit, in which a sub-board, provided with short-circuiting wiring, is mounted on the burn-in board to override the operation of a plural number of pull-up resistors connected to a lead terminal. The universal burn-in board, shown in the above gazette, is provided with a large number of pull-up resistors for pull-up of the input and output terminals for protecting the device.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2002-314394A
[Patent Document 2]
JP Patent Kokai Publication No. JP-A-7-58172